The present invention relates to a semiconductor device and method of manufacturing the same, a circuit board and an electronic instrument.
Conventionally, the underlying metal of solder bumps is formed by a barrier metal thin film directly formed on the electrode (normally aluminum) and formed at substantially the same size, and a metal thin film formed directly on the barrier metal thin film at substantially the same size and with good wettability with solder. The same construction is used, even when an interconnect layer is formed on a semiconductor chip.
In recent years, with the more compact design of electronic instruments, there has been an active move toward directly connecting a semiconductor device having solder bumps to the substrate, to provide even more compact and lightweight electronic instruments. In view of this, there is an increasing demand for a reliable connection of the semiconductor chip to a substrate with a greatly differing coefficient of thermal expansion. For example, as disclosed in Japanese Patent Publication No. 7-105586, a construction has been proposed whereby the underlying metal of substantially the same size as the solder bumps is formed as a multilayer metal layer providing stress relief.
However, for the actual connection of the semiconductor device, the are problems of the process becoming complicated or additional materials cost being incurred, because for example the mounting is on a substrate restricted to having a coefficient of thermal expansion close to that of the semiconductor chip, or the semiconductor chip is limited in size, or after the connection an additional step of injecting resin is required.
The present invention solves the above problems, and has as its object the provision of a semiconductor device and method of manufacture thereof, a circuit board and an electronic instrument such that without requiring selection of the substrate material or additional steps after connection, connection reliability can be assured, direct connection to a substrate is possible, and further an electronic instrument can be made more compact and lightweight.
(1) A semiconductor device of the present invention comprises:
a semiconductor chip having electrodes;
an interconnect layer connected to the electrodes;
a conducting layer formed on the interconnect layer, avoiding a position where the electrodes are provided;
an underlying metal layer formed on the conducting layer, the underlying metal layer having a size larger than a peripheral outline of the conducting layer, and being more easily deformed than the conducting layer;
a bump formed on the underlying metal layer; and
a resin layer (insulating protection layer) formed around the conducting layer.
According to the present invention, as the conducting layer is deformed by thermal stress, so the underlying metal layer also deforms. Since a resin layer is provided around the conducting layer, the large part of the thermal stress is applied to the underlying metal layer rather than the conducting layer, and since the underlying metal layer can be greatly deformed, the thermal stress can be absorbed. As a result, the force applied by thermal stress on the conducting layer is reduced, and failure of conduction by shearing of the conducting layer can be suppressed.
(2) In this semiconductor device,
the bump may be formed having a size larger than the peripheral outline of the conducting layer; and
a projected area of a region in which the bump contacts with the underlying metal layer may be larger than a projected area of a region in which the underlying metal layer contacts with the conducting layer.
(3) In this semiconductor device,
the resin layer may contact at least a portion of a lower surface of the underlying metal layer.
(4) In this semiconductor device,
wherein the resin layer may be formed being separated from a lower surface of the underlying metal layer.
(5) In this semiconductor device,
an adhesive may be provided between the lower surface of the underlying metal layer and the resin layer.
(6) In this semiconductor device,
the conducting layer may have a height approximately in a range 12 to 300 xcexcm, and a diameter approximately in a range 20 to 100 xcexcm.
By means of this, since the conducting layer is easily deformed, the thermal stress can be efficiently absorbed.
(7) A circuit board of the present invention has the above-described semiconductor device mounted thereon.
(8) An electronic instrument of the present invention is equipped with the above-described semiconductor device.
(9) A method of manufacturing a semiconductor device of the present invention comprises:
a step of preparing a semiconductor chip having electrodes and an interconnect layer connected to the electrodes;
a step of forming a conducting layer on the interconnect layer, avoiding a position where the electrodes are provided;
a step of forming an underlying metal layer on the conducting layer, the underlying metal layer having a size larger than a peripheral outline of the conducting layer, and being more easily deformed than the conducting layer;
a step of forming a bump on the underlying metal layer; and
a step of forming a resin layer around the conducting layer.
With a semiconductor device manufactured according to the present invention, as the conducting layer is deformed by thermal stress, so the underlying metal layer also deforms.
Since a resin layer is provided around the conducting layer, the large part of the thermal stress is applied to the underlying metal layer rather than the conducting layer, and since the underlying metal layer can be greatly deformed, the thermal stress can be absorbed. As a result, the force applied by thermal stress on the conducting layer is reduced, and failure of conduction by shearing of the conducting layer can be suppressed.
(10) In this method of manufacturing a semiconductor device,
the steps of forming the conducting layer and the resin layer may comprise:
a first step of providing an opening in a formation of the resin layer, as a formation region for the conducting layer, on the interconnect layer;
a second step of filling the opening by a printing method with a conductive paste having a conductive filler distributed in a binder; and
a third step of heating the conductive paste and hardening the, binder, to cause the binder intimate contact with the interconnect layer.
By means of this, the opening of the resin layer can easily be filled with the conductive paste by a printing method.
(11) In this method of manufacturing a semiconductor device,
in the third step, the conductive filler may be fused, to cause intimate contact with the interconnect.
By means of this, since the conductive filler is fused, a conducting layer in intimate contact with the interconnect can be formed.
(12) In this method of manufacturing a semiconductor device,
the step of forming the underlying metal layer may comprise:
after forming the conducting layer and the resin layer, a first step of adhering a metal foil provided with an adhesive avoiding a contact portion with the conducting layer on the conducting layer and the resin layer in a vacuum, creating a vacuum in a space between the conducting layer and the metal foil at atmospheric pressure, and bringing the conducting layer and the metal foil into intimate contact; and
a second step of patterning the metal foil in a form of the underlying metal layer.
By means of this, by adhering and patterning the metal foil, the underlying metal layer can be formed easily.
(13) In this method of manufacturing a semiconductor device,
the step of forming the conducting layer and the underlying metal layer may comprise:
a first step of providing a first conducting material in a region including a formation region of the conducting layer;
a second step of forming a first resist layer having a first opening which is provided at a formation region of the conducting layer and positioned on the first conducting material;
a third step of providing a second conducting material within the first opening and on the first conducting material;
a fourth step of forming on the first resist layer a second resist layer having a second opening formed at a formation region of the underlying metal layer;
a fifth step of providing a metal material in the second opening to form the underlying metal layer; and
a sixth step of removing the first and second resist layers, patterning the first conducting material, and forming the conducting layer from a portion of the first conducting material and the second conducting material.